1. Field of the Invention
The present invention relates to a built-in self-test system, more particularly, to an input/output (I/O) circuit, and to a semiconductor integrated circuit, capable of performing a self-test.
2. Description of the Related Art
In respect to an I/O circuit transmitting and receiving data via a port, the technique to transmit and receive the data with a clock as a synchronizing signal has been proposed. In the technique of transmitting and receiving the data with the clock, when a transfer rate increases, a phase error is generated between each phase of the data and the clock. For this reason, the technique of only transmitting and receiving data is usually adopted when the transfer rate is high. In case of testing a semiconductor integrated circuit integrating the I/O circuit, the technique of testing the I/O circuit by feeding back output data supplied by an output terminal to an input terminal is known (hereinafter referred to as “a loop-back test”). Furthermore, the technique of integrating a test circuit on a semiconductor chip has been proposed (hereinafter referred to as “a built-in self-test (BIST)”).
With respect to the loop-back test, occurrence of an error is tested by supplying the output data to the input terminal for a fixed period. A guarantee value of a signal-receiving circuit is an error rate of less than or equal to 10−12 bits. In this case, more than 5 minutes is necessary to transmit 1012 bits of data bit at a rate of 3.2 [Gbps]. As described above, decrease of test efficiency of a semiconductor integrated circuit occurs since test time increases.